Prof. Andrzej Napieralski
Head of Department of Microelectronics and Computer Science

Department of Microelectronics and Computer Science joined Cadence Academic Network in 2008. Since then we have been working closely with Cadence to increase our know-how in the field of integrated circuit design especially in digital and mixed-signal areas. We are open to any collaboration opportunities from industry and academia.

Contact

Adrian Rominski - Academic Network Coordinator at TUL
Lukasz Kotynia

Education

The list of classes where Cadence tools are used:

• Microelectronics (English lang. course)
• Podstawy Mikroelektroniki (Basics of Microelectronics)
• Podstawy Mikroelektroniki (Basics of Microelectronics) non-stationary, weekend courses
• Wstęp do SystemĂłw Cyfrowych i Mikroelektroniki (Introduction to Microelectronics & Digital Systems) non-stationary, weekend courses
• Recent Technological Advances (English lang. course)

For students:
Cadence Design Systems offers internship opportunities for our students in one of its European office (UK, Germany). If you're interested please contact Lukasz Kotynia or Adrian Rominski

Events and acheivements

Current conferences and other events:

• 17th International Conference Mixed Design of Integrated Circuits and Systems Wroclaw, 24-26 June 2010

Past events:

• IDESA Advanced Physical implementation flow held in Lodz between September 28th and October 2nd, 2009
• Cadence AMS Methodology Kit held in Lodz between February 10th and February 12th, 2009

Our staff and students have won many awards on international conferences and international trade fairs including the first prize at Student Design Contest at CDNLive! EMEA 2008 for Lukasz Kotynia (official press release). The complete list can be found here.

Research

We successfully used Cadence tools during our scientific research activities. Here you can find our latest achievements.

PERPLEXUS

PERPLEXUS (Pervasive computing framework for modeling complex virtually-unbounded systems - VI FP, Contract Number 034632). The chip contains 10x10 array of configurable blocks. Its is a prototype of dynamically reconfigurable FPGA supporting self-replication and auto-routing mechanisms. Configurable blocks contain also small ALUs, thus the chip can work as a multi-core processor.

Chip Details:
Process: UMC 180 nm CMOS
Area: 50 sqmm
Production: 2009

The complete list of ASIC designed in our Department can be found here.

External links

Here you can find pieces of information that we found interesting while working on our  teaching and research tasks. We put them into several categories:

• Low Power Design
• Getting started with synthesis using Encounter RTL Compiler
• Getting started with Place and Route using Encounter Digital Implementation System
• Additional information related to digital hierarchical flow
• Getting started with AMS Designer
• Digital/Analog Mixed Signal methodologies
• Behavioral Modeling of MS blocks
• Parasitic Aware Simulation flow

Please do not hesitate to contact us if you have any questions or suggestions.
Important: Cadence Online Support (COS) login may be required to access some of the materials below like Cadence Video Library containing a list of videos/webinars showing Cadence tools and solutions.

• Low Power Design
•  The Power Forward Initiative (PFI) - including Low Power Design Guide  
  
•  CPF Specification - including specification, tutorials and training materials
• Getting started with synthesis using Encounter RTL Compiler
•  Encounter RTL Compiler Synthesis Flows documentation - RC_install_dir/doc/rc_start/
•  write_template command in Command Reference for Encounter RTL Compiler
• Getting started with Place and Route using Encounter Digital Implementation System
• Workshops shipped with the tool - EDI_install_dir/share/fe/gift/tutorials/dtmf
  Note: Before you can run the workshops, you must download the Artisan Libraries.  The download information is found in the workshop instructions.(Section 2: #2)
• EDI Foundation Flow demos
• Flat
• Hierarchical
• Low Power
• Advanced
• Additional information related to hierarchical flow
• Chapters from Encounter Digital Implementation System User Guide
• ILM - Using Interface Logic Models in Hierarchical Designs
• ART - Using ART in Hierarchical Designs
• What-If Timing Analysis
• Extracting Timing Models (ETM)
• Getting started with AMS Designer
• Tutorials shipped with the software - IC61_install_dir/tools/dfII/samples/tutorials/AMS - including Workshop for AMSD Virtuoso Use Model
• Digital/Analog Mixed Signal methodologies
• MSoT Mixed Signal Physical Implementation using EDI & Virtuoso
• DoT Mixed Signal Physical Implementation using EDI & Virtuoso
• AoT Mixed Signal Physical Implementation using EDI, Virtuoso & CSR
• Mixed-Signal Simulation for Analog Designers webinar
• Slides
  Important: Slide 22 gives reference to other videos
• Video
• Static Timing Analysis for Mixed-Signal Designs
• Encounter Digital Implementation System User Guide
• Solution Flow Application Note
• Mixed-Signal Behavioral Modeling
• The Designer's Guide Community
• VerilogA models shipped with the tools -  IC_install_dir/tools/dfII/samples/artist/spectreHDL/Verilog-A/
• Design Characterization and Modeling(DCM) - generation, verification and calibration of Verilog-A[MS]. VHDL-AMS, Verilog-D and Liberty behavioral models
• Virtuoso Analog Design Environment GXL User Guide documentation
• Tutorials/examples shipped with the software -  IC61_install_dir/tools.lnx86/dfII/samples/dcm - including:
• AMS Design and Model Validation (amsDmv)
• Virtuoso DCM RF baseband models (RF)
• Virtuoso Design and Characterization and Modeling labs/training (dcm_lab.tar.Z)
  Create a calibrated Verilog-A or Liberty .lib using ADE GXL results
• Parasitic Aware Simulation flow
• Virtuoso Parasitic Aware Design User Guide documentation
• Using Parasitic Estimate demo

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